268 lines
14 KiB
C#
268 lines
14 KiB
C#
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using System;
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using Unity.Burst;
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#if !BURST_INTERNAL
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using AOT;
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using UnityEngine;
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#endif
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using System.Runtime.InteropServices;
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namespace Unity.Burst.Intrinsics
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{
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#if !BURST_INTERNAL
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[BurstCompile]
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#endif
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public unsafe static partial class X86
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{
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/// <summary>
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/// The 32-bit MXCSR register contains control and status information for SSE and AVX SIMD floating-point operations.
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/// </summary>
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[Flags]
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public enum MXCSRBits
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{
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/// <summary>
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/// Bit 15 (FTZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD floating-point underflow condition.
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/// </summary>
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/// <remarks>
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/// When the underflow exception is masked and the flush-to-zero mode is enabled, the processor performs the following operations when it detects a floating-point underflow condition.
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/// - Returns a zero result with the sign of the true result
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/// - Sets the precision and underflow exception flags.
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///
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/// If the underflow exception is not masked, the flush-to-zero bit is ignored.
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///
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/// The flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-mandated masked response to under-flow is to deliver the denormalized result.
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/// The flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster execution can be achieved for applications where underflows
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/// are common and rounding the underflow result to zero can be tolerated. The flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode.
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/// </remarks>
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FlushToZero = 1 << 15,
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/// <summary>
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/// Mask for rounding control bits.
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/// </summary>
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///
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/// The rounding modes have no effect on comparison operations, operations that produce exact results, or operations that produce NaN results.
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RoundingControlMask = (1 << 14) | (1 << 13),
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/// <summary>
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/// Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is the even value (that is, the one with the least-significant bit of zero). Default.
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/// </summary>
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RoundToNearest = 0,
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/// <summary>
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/// Rounded result is closest to but no greater than the infinitely precise result.
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/// </summary>
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RoundDown = (1 << 13),
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/// <summary>
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/// Rounded result is closest to but no less than the infinitely precise result.
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/// </summary>
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RoundUp = (1 << 14),
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/// <summary>
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/// Rounded result is closest to but no greater in absolute value than the infinitely precise result.
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/// </summary>
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RoundTowardZero = (1 << 13) | (1 << 14),
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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PrecisionMask = 1 << 12,
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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UnderflowMask = 1 << 11,
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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OverflowMask = 1 << 10,
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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DivideByZeroMask = 1 << 9,
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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DenormalOperationMask = 1 << 8,
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/// <summary>Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked.</summary>
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InvalidOperationMask = 1 << 7,
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/// <summary>
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/// Combine all bits for exception masking into one mask for convenience.
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/// </summary>
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ExceptionMask = PrecisionMask | UnderflowMask | OverflowMask | DivideByZeroMask | DenormalOperationMask | InvalidOperationMask,
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/// <summary>
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/// Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response to a SIMD floating-point denormal operand condition.
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/// </summary>
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///
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/// When the denormals-are-zeros flag is set, the processor converts all denormal source operands to a zero with the sign of the original operand before performing any computations on them.
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/// The processor does not set the denormal-operand exception flag (DE), regardless of the setting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand
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/// exception if the exception is unmasked.The denormals-are-zeros mode is not compatible with IEEE Standard 754.
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///
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/// The denormals-are-zeros mode is provided to improve processor performance for applications such as streaming media processing, where rounding a denormal operand to zero does not
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/// appreciably affect the quality of the processed data. The denormals-are-zeros flag is cleared upon a power-up or reset of the processor, disabling the denormals-are-zeros mode.
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///
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/// The denormals-are-zeros mode was introduced in the Pentium 4 and Intel Xeon processor with the SSE2 extensions; however, it is fully compatible with the SSE SIMD floating-point instructions
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/// (that is, the denormals-are-zeros flag affects the operation of the SSE SIMD floating-point instructions). In earlier IA-32 processors and in some models of the Pentium 4 processor, this flag
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/// (bit 6) is reserved. Attempting to set bit 6 of the MXCSR register on processors that do not support the DAZ flag will cause a general-protection exception (#GP).
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DenormalsAreZeroes = 1 << 6,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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PrecisionFlag = 1 << 5,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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UnderflowFlag = 1 << 4,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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OverflowFlag = 1 << 3,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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DivideByZeroFlag = 1 << 2,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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DenormalFlag = 1 << 1,
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/// <summary>Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them.</summary>
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InvalidOperationFlag = 1 << 0,
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/// <summary>
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/// Combines all bits for flags into one mask for convenience.
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/// </summary>
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FlagMask = PrecisionFlag | UnderflowFlag | OverflowFlag | DivideByZeroFlag | DenormalFlag | InvalidOperationFlag,
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}
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/// <summary>
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/// Rounding mode flags
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/// </summary>
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[Flags]
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public enum RoundingMode
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{
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/// <summary>
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/// Round to the nearest integer
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/// </summary>
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FROUND_TO_NEAREST_INT = 0x00,
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/// <summary>
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/// Round to negative infinity
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/// </summary>
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FROUND_TO_NEG_INF = 0x01,
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/// <summary>
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/// Round to positive infinity
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/// </summary>
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FROUND_TO_POS_INF = 0x02,
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/// <summary>
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/// Round to zero
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/// </summary>
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FROUND_TO_ZERO = 0x03,
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/// <summary>
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/// Round to current direction
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/// </summary>
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FROUND_CUR_DIRECTION = 0x04,
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/// <summary>
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/// Do not suppress exceptions
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/// </summary>
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FROUND_RAISE_EXC = 0x00,
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/// <summary>
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/// Suppress exceptions
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/// </summary>
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FROUND_NO_EXC = 0x08,
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/// <summary>
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/// Round to the nearest integer without suppressing exceptions
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/// </summary>
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FROUND_NINT = FROUND_TO_NEAREST_INT | FROUND_RAISE_EXC,
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/// <summary>
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/// Round using Floor function without suppressing exceptions
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/// </summary>
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FROUND_FLOOR = FROUND_TO_NEG_INF | FROUND_RAISE_EXC,
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/// <summary>
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/// Round using Ceiling function without suppressing exceptions
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/// </summary>
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FROUND_CEIL = FROUND_TO_POS_INF | FROUND_RAISE_EXC,
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/// <summary>
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/// Round by truncating without suppressing exceptions
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/// </summary>
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FROUND_TRUNC = FROUND_TO_ZERO | FROUND_RAISE_EXC,
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/// <summary>
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/// Round using MXCSR.RC without suppressing exceptions
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/// </summary>
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FROUND_RINT = FROUND_CUR_DIRECTION | FROUND_RAISE_EXC,
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/// <summary>
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/// Round using MXCSR.RC and suppressing exceptions
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/// </summary>
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FROUND_NEARBYINT = FROUND_CUR_DIRECTION | FROUND_NO_EXC,
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/// <summary>
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/// Round to nearest integer and suppressing exceptions
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/// </summary>
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FROUND_NINT_NOEXC = FROUND_TO_NEAREST_INT | FROUND_NO_EXC,
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/// <summary>
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/// Round using Floor function and suppressing exceptions
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/// </summary>
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FROUND_FLOOR_NOEXC = FROUND_TO_NEG_INF | FROUND_NO_EXC,
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/// <summary>
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/// Round using Ceiling function and suppressing exceptions
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/// </summary>
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FROUND_CEIL_NOEXC = FROUND_TO_POS_INF | FROUND_NO_EXC,
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/// <summary>
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/// Round by truncating and suppressing exceptions
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/// </summary>
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FROUND_TRUNC_NOEXC = FROUND_TO_ZERO | FROUND_NO_EXC,
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/// <summary>
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/// Round using MXCSR.RC and suppressing exceptions
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/// </summary>
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FROUND_RINT_NOEXC = FROUND_CUR_DIRECTION | FROUND_NO_EXC,
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}
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internal struct RoundingScope : IDisposable
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{
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private MXCSRBits OldBits;
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public RoundingScope(MXCSRBits roundingMode)
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{
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OldBits = MXCSR;
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MXCSR = (OldBits & ~MXCSRBits.RoundingControlMask) | roundingMode;
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}
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public void Dispose()
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{
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MXCSR = OldBits;
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}
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}
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#if !BURST_INTERNAL
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private static void BurstIntrinsicSetCSRFromManaged(int _) { }
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private static int BurstIntrinsicGetCSRFromManaged() { return 0; }
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internal static int getcsr_raw() => DoGetCSRTrampoline();
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internal static void setcsr_raw(int bits) => DoSetCSRTrampoline(bits);
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[BurstCompile(CompileSynchronously = true)]
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private static void DoSetCSRTrampoline(int bits)
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{
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if (Sse.IsSseSupported)
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BurstIntrinsicSetCSRFromManaged(bits);
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}
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[BurstCompile(CompileSynchronously = true)]
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private static int DoGetCSRTrampoline()
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{
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if (Sse.IsSseSupported)
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return BurstIntrinsicGetCSRFromManaged();
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return 0;
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}
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#elif BURST_INTERNAL
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// Internally inside burst for unit tests we can't recurse from tests into burst again,
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// so we pinvoke to a dummy wrapper DLL that exposes CSR manipulation
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[DllImport("burst-dllimport-native", EntryPoint = "x86_getcsr")]
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internal static extern int getcsr_raw();
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[DllImport("burst-dllimport-native", EntryPoint = "x86_setcsr")]
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internal static extern void setcsr_raw(int bits);
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#endif
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/// <summary>
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/// Allows access to the CSR register
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/// </summary>
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public static MXCSRBits MXCSR
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{
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[BurstTargetCpu(BurstTargetCpu.X64_SSE2)]
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get
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{
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return (MXCSRBits)getcsr_raw();
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}
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[BurstTargetCpu(BurstTargetCpu.X64_SSE2)]
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set
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{
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setcsr_raw((int)value);
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}
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}
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}
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}
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